1. Field of the Invention
The present invention relates to electronics. More specifically, the present invention relates to digital to analog converters.
2. Description of the Related Art
Digital to analog converters are widely used for converting digital signals to corresponding analog signals for many electronic circuits. For example, a high resolution, high speed digital to analog converter (DAC) may find application in video circuits, high quality audio, instrumentation applications, and in the transmit path for high dynamic range communications applications. It may also be used in high speed analog to digital converters (ADCs) that utilize DACs such as successive approximation ADCs or subranging ADCs.
A common type of DAC, the current summing DAC, generates an analog output signal by selectively switching a number of current sources (or cells) into or out of a current summing device in response to a digital input signal. Because of process variables, the multiple current sources required by the DAC cannot be fabricated to exact values. In fact, current sources can vary from one to the next, even on the same die. These inaccuracies result in distortions in the analog output signal. The current sources therefore need to be trimmed to meet the accuracy requirements of the DAC. They can be trimmed to equal one another (unary DACs) or to provide currents with binary weights (binary DACs).
The prior art accomplished this trimming in various ways. The most straightforward method used is to trim the current setting resistors of the current sources with a laser, in effect changing the value of the resistor chain by burning material off to raise the resistance. This technique has several problems. One significant problem is that an expensive trimming laser system must be used. In addition, this process can only be done prior to packaging and therefore will not be able to correct for any post-trim stresses the chip might encounter during cleaning, packaging and sealing. Because the resistors are subject to change when stressed, they must be placed on the chip in locations that will minimize the stress they experience. This impacts and limits the IC layout. There are also issues with time since the trim process must be approached linearly (i.e., a binary search cannot be used). This, of course, adds costs to the device. Furthermore, any mistakes made by the laser trimming process cannot be done. If too much of a resistor is trimmed off, all of the resistors will need to be retrimmed.
There are other approaches that allow for resistor trimming, but they generally require significant pad areas because of the high voltages and/or currents required to blow fuse links. These restrictions limit the number of corrections that can be made, thereby limiting the overall resolution or dynamic range of the DAC.
Another approach is to add a second variable current source to each cell to make the total steered current correct to the accuracy required. The variable current source can be trimmed over a small range of current to allow for the required adjustment to be made. For each current source to be adjusted (and there are typically several), an extra node is connected to each current summing bus. This extra loading on the current bus will impact the settling time of the DAC and slow down its operating speed. This is not acceptable in many applications.
Hence, there is a need in the art for an improved system or method for trimming current sources in digital to analog converters that overcomes the shortcomings of prior art approaches.